Blocking assignment and nonblocking assignment is one of the most misunderstood constructs in Verilog HDL, which usually bewilders the designer of FPGA.
阻塞赋值与非阻塞赋值语句作为verilog HDL语言的最大难点之一,一直困扰着FPGA设计者,而其中的错误又隐晦莫测,理解不透彻会直接导致运用不当,使设计工程达不到预期效果,而排错又相当麻烦。
Blocking assignment and nonblocking assignment is one of the most misunderstood constructs in Verilog HDL, which usually bewilders the designer of FPGA.
阻塞赋值与非阻塞赋值语句作为verilog HDL语言的最大难点之一,一直困扰着FPGA设计者,而其中的错误又隐晦莫测,理解不透彻会直接导致运用不当,使设计工程达不到预期效果,而排错又相当麻烦。
