The principle of the proposed technique is firstly to utilize automatic test pattern generator tools to generate deterministic test patterns with short length and high fault coverage, then the generated patterns are sorted to get low power test sequence, and finally the BIST circuit description is automatically generated by selecting finite state machine optimiz.
先对原型设计用自动测试图形工具生成长度短、故障覆盖率高的确定性测试图形,然后对生成的图形排序以取得低功耗测试序列,再选择状态机优化和综合方案,最后自动生成BIST电路描述。
